These Integrated Circuits contain two independent D-type positive-edge triggered flip flop circuits. A low level at the preset or clear input pins set or resets the outputs regardless of the levels of the other inputs. When preset and clear are disabled (high logic level), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.